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d <= b[a-:3] is correct. See 7.4.6 Indexing and slicing of arrays in the 1800-2012 LRM. All Verilog bit vector widths must be determined at compile time. Even though it seems that you could prove that [a:a-2] would have a constant width, that's too much work for a compiler to verify for general expressions.
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Thanks for the correction.
I don't think that it's too much for a compiler to verify, VHDL e.g. accepts similar expressions where both range limits are calculated. I believe that those people who designed Verilog tried to avoid unnecessary compiler effort with the explicite indexed part-select syntax. The construct also fits the Verilog typical shorthand style (in contrast to verbose VHDL). Now it's convention and has to be learned when picking up Verilog.
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