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Altera_Forum
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11 years ago

May I use a reg variable to indicate the bus bit ?

I have a design, I want to use a reg variable to control another bus bit like&#65306; reg [2:0] a; reg [7:0] b; reg c; reg [2:0] d; case 1: c <= b[a]; case 2: d <= ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

d <= b[a-:3] is correct. See 7.4.6 indexing and slicing of arrays in the 1800-2012 LRM. All Verilog bit vector widths must be determined at compile time. Even though it seems that you could prove that [a:a-2] would have a constant width, that's too much work for a compiler to verify for general expressions.