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Altera_Forum
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11 years ago

May I use a reg variable to indicate the bus bit ?

I have a design, I want to use a reg variable to control another bus bit like&#65306; reg [2:0] a; reg [7:0] b; reg c; reg [2:0] d; case 1: c <= b[a]; case 2: d <= ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Review your Verilog text book or Verilog LRM about indexed part-select syntax

e.g. 

d <= b;

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Thanks very much, FvM. But based on your explanation, I think it should be :

d <= b[a-:3]

since 'd' is 3 bits wide.

Correct?

Thanks.