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Altera_Forum's avatar
Altera_Forum
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13 years ago

Maximum frequency with QuartusII

Hi everyone,

I have a simple question from an expert of the EDA tools. If I set a fmax of say 300 MHz and the QuartusII STA reports the fmax achieved is 280MHz. The STA also provides a list of failing paths. If suppose I change the fmax to 275MHz and run only the STA without recompiling the whole design for the new fmax. The STA will provide no failing paths for this fmax. Will this image work in FPGA at the new fmax. I haven't yet tried this into the FPGA for non availability of the test board. I think it should work.

Thanks,

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Yes, it will. I would recommend running Processing -> Start -> TimeQuest, which will run the full TQ flow, i.e. it will analyze all timing models which is a normal part of sign-off flow, but if it passes you're good to go. (Another example I see is a design failing timing, and the user realizes the failing paths can be false path'd or multicycled. They change the .sdc, re-run TQ, and if it passes they're good...)