Forum Discussion
ESkul1
New Contributor
New ContributorMAX10 set_false_path failure
Attempted to add CDC module (VHDL) with the following attributes applied (taken from Intel/Altera example): ATTRIBUTE altera_attribute : string; ATTRIBUTE altera_attribute OF ff1 : signal is "-...
KennyT_altera
Super Contributor
Super ContributorCan you try to put this constrain in the sdc files?
go to File -> new -> other files -> Synonopsis Design File
Right click on it and insert the command that you want.
Compile the design to see if it still got ignored.
If no, use this way instead of using an Attribute.
