New Contributor
Super ContributorAny time code is changed, a new "seed" is used for the compilation which can produce different results. Is something changing that is causing your design to not work when you recompile (timing failure, inappropriate resource usage, etc.)? If so, it may be better to look and try to debug the issue instead of relying on compiling with a seed that meets your requirements.
New ContributorLike I said, sometimes simply recompiling without touching the code is also producing different results on fusing to the FPGA. This is what troubles us the most. How can this be avoided? Let us know what settings to use to prevent this.
