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BOnor's avatar
BOnor
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7 years ago

MAX10 GPIO Lite DDR Output Sim

I've run into the follow error while initializing an Aldec simulation: ELBREAD: Error: ELBREAD_0081 fiftyfivenm_atoms_ncrypt.v (732): Design unit protected_97b98e91bb4cae2ac97c0cd96c2469e5 instantia...
MuhammadAr_U_Intel's avatar
MuhammadAr_U_Intel
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7 years ago

Hi Brian,

"altera_ver" is a Altera simulation library for Verilog similarly there is one for VHDL "altera" and is needed to simulate the IP. I am wondering if this is not part of auto-generated script.

I am glad you are able to proceed.

Thanks,

Arslan