New Contributor
New ContributorI have already tried to use the auto-generate simulation script which creates and compiles all of the required libraries.
I've also tried the pre-compiled Aldec libraries. Same results in both cases.
When the issue first started I was using Active-HDL 10.3 and Quartus 17.0.
Then I updated to the latest of both tools: Active-HDL 10.5a.12.6914 and Quartus 18.1.0
gpoutputddr_inst : component altera_gpio_lite
generic map (
PIN_TYPE => "output",
SIZE => 1,
REGISTER_MODE => "ddr",
BUFFER_TYPE => "single-ended",
ASYNC_MODE => "clear",
SYNC_MODE => "none",
BUS_HOLD => "false",
OPEN_DRAIN_OUTPUT => "false",
ENABLE_OE_PORT => "false",
ENABLE_NSLEEP_PORT => "false",
ENABLE_CLOCK_ENA_PORT => "false",
SET_REGISTER_OUTPUTS_HIGH => "false",
INVERT_OUTPUT => "false",
INVERT_INPUT_CLOCK => "false",
USE_ONE_REG_TO_DRIVE_OE => "false",
USE_DDIO_REG_TO_DRIVE_OE => "false",
USE_ADVANCED_DDR_FEATURES => "false",
USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY => "false",
ENABLE_OE_HALF_CYCLE_DELAY => "true",
INVERT_CLKDIV_INPUT_CLOCK => "false",
ENABLE_PHASE_INVERT_CTRL_PORT => "false",
ENABLE_HR_CLOCK => "false",
INVERT_OUTPUT_CLOCK => "false",
INVERT_OE_INCLOCK => "false",
ENABLE_PHASE_DETECTOR_FOR_CK => "false"
)
port map (
outclock => outclock, -- outclock.export
din => din, -- din.export
pad_out => pad_out, -- pad_out.export
aclr => aclr, -- aclr.export
outclocken => '1', -- (terminated)
inclock => '0', -- (terminated)
inclocken => '0', -- (terminated)
fr_clock => open, -- (terminated)
hr_clock => open, -- (terminated)
invert_hr_clock => '0', -- (terminated)
phy_mem_clock => '0', -- (terminated)
mimic_clock => open, -- (terminated)
dout => open, -- (terminated)
pad_io => open, -- (terminated)
pad_io_b => open, -- (terminated)
pad_in => "0", -- (terminated)
pad_in_b => "0", -- (terminated)
pad_out_b => open, -- (terminated)
aset => '0', -- (terminated)
sclr => '0', -- (terminated)
nsleep => "0", -- (terminated)
oe => "0" -- (terminated)
);
Thanks for the support!
-Brian
