Forum Discussion
NM8
New Contributor
New ContributorMAX10 FPGA Pin Assignments for LVDS signals input and outputs
Hi, We are using MAX10 FPGA(10M40SCE144C8G) with our board. We want to connect multiple input and output LVDS signals to one of the banks of this FPGA. To use the true LVDS (TX or RX) should we use...
Hi Nanjunda,
I tried to replicate scenario & I observed the below results,please try to implement same at your end & if you have any different issue,let me know,
please find the below link & attachments,
https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html#sam1394435423058
Regards,
Vikas
Vicky1
Regular Contributor
Regular ContributorHi Nanjunda,
I tried to replicate scenario & I observed the below results,please try to implement same at your end & if you have any different issue let me know,
please find the below link & attachments,
https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html#sam1394435423058
Regards,
Vikas
NM8Hi Vikas,
Not sure what you are referring to in the link above.
Are you referring to "Intel MAX 10 LVDS SERDES I/O Standards Support " heading?
I do want to use the True LVDS & I'm clear with the pins to be used for it.
Just that confusion whether to give VCCO=2.5V or 3.3V.
I hope you can clear it. If you recommend to use 2.5V, why not 3.3V and what would be the signal characteristics with 3.3V VCCO.
Thanks & Regards,
Nanjunda M
