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NM8's avatar
NM8
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7 years ago
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MAX10 FPGA Pin Assignments for LVDS signals input and outputs

Hi, We are using MAX10 FPGA(10M40SCE144C8G) with our board. We want to connect multiple input and output LVDS signals to one of the banks of this FPGA. To use the true LVDS (TX or RX) should we use...
Abe's avatar
Abe
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7 years ago

Well, I just took a look at your pin assignments and see that you have assigned a single IO Bank (Bank 2) with both 3.3V LVCMOS as well as 3.0V LVCMOS. This is a violation of the Bank IO standard rule I mentioned earlier.

You can only assign one IO standard/voltage to a Bank. Assign the single-ended pins that need a different voltage standard , for eg, 3.0V or 2.5V to another bank and assign the pins accordingly.

Either Change the voltage standard for the EXTR1 pin to 3.3V LVCMOS or move to another Bank and Pin location.

NM8's avatar
NM8
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7 years ago

Hi Abe,

Sorry for that. Can you please change the standard to 3.3V LVCMOS and assign any pin in same bank(bank2) and compile.

You will see the error I have stated in previous email. I have tried, (Do not forget to check the pin assignment if the compilation passes)

Kindly try once and let me know the results of compilation.

Thanks & Regards

Nanjunda M