MAX10 FPGA Pin Assignments for LVDS signals input and outputs

Hi Abe,

FYI the project is attached. You can compile it and check.

The errors are as below:

""Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

Warning (176674): Following 2 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.

Warning (176118): Pin "MX_REFCLK_100MP" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "MX_REFCLK_100MP(n)"

Warning (176118): Pin "CE2_MX_CLKP" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "CE2_MX_CLKP(n)"

Error (169236): Can't place I/O pin Extr1 in assigned location IOBANK_2 made by User Location Constraints source

Error (169027): Pin Extr1 is incompatible with I/O bank 2. Pin uses I/O standard 3.0-V LVCMOS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or other pins that use I/O standard LVDS.

Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00

Error (171000): Can't fit design in device

Warning (169177): 1 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

Info (169178): Pin MXFPGA_RESETIN uses I/O standard 3.3-V LVCMOS at 27

Warning (169069): Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results

Info (169070): Pin Extr1 has GND driving its datain port

Error: Quartus Prime I/O Assignment Analysis was unsuccessful. 3 errors, 9 warnings

Error: Peak virtual memory: 5003 megabytes

Error: Processing ended: Tue Mar 05 13:36:59 2019

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:02"

Thanks & Regards,

Nanjunda M