Forum Discussion

NM8's avatar
NM8
Icon for New Contributor rankNew Contributor
7 years ago
Solved

MAX10 FPGA Pin Assignments for LVDS signals input and outputs

Hi, We are using MAX10 FPGA(10M40SCE144C8G) with our board. We want to connect multiple input and output LVDS signals to one of the banks of this FPGA. To use the true LVDS (TX or RX) should we use...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Yes, you can. I have compiled an LVDS design using both LVDS Tx & Rx @ Bank3 and IO Standard set to 3.3 V LVCMOS. But make sure to set all other pins in the same Bank to the same voltage standard.

The design I used has single-ended signals also at the same bank set to 3.3V LVCMOS.

Can you post the compilation report file here.. so we can take a look and see whats wrong. As well as the pin assignments file QSF.

  • NM8's avatar
    NM8
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi Abe,

    Thanks a lot for your inputs.

    "I have compiled an LVDS design using both LVDS Tx & Rx @ Bank3 and IO Standard set to 3.3 V. But make sure to set all other pins in the same Bank to the same voltage standard."

    I tried the same thing. My experiment results are as below:

    1. With just LVDS TX & RX with VCCIO=3.3V - Compilation passed
    2. Along with '1' I added 1 input single ended (defined as 3.3V LVCMOS in Assignment editor) signal to the same bank - Compilation passed
    3. Along with '2' I added 1 output single ended (defined as 3.3V LVCMOS in Assignment editor) signal to the same bank - Compilation failed.

    Got an error saying there is no IO voltage compatibility between the IO pins.

    According to your statement above, we are still working all at 3.3V level, yet we get a error which says we are not right.

    Could you give me some confirmation on this please?

    Thanks & Regards,

    Nanjunda M