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NM8's avatar
NM8
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7 years ago
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MAX10 FPGA Pin Assignments for LVDS signals input and outputs

Hi, We are using MAX10 FPGA(10M40SCE144C8G) with our board. We want to connect multiple input and output LVDS signals to one of the banks of this FPGA. To use the true LVDS (TX or RX) should we use...
Abe's avatar
Abe
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7 years ago

You cannot assign a single IO bank with both 3.3V and 2.5V IO standards. If you assign Bank1 for 2.5V IO then all the IO in this bank will share the same IO standard. This is coz the VccIO for that particular Bank will have to be set to 2.5V.

You will have to assign the 2.5V and 3.3V signals to different IO banks and then compile. Plus also make sure that the IO bank you are planning to use for LVDS does support the LVDS standard (True-LVDS/BLVDS/Emulated LVDS/mini-LVDS/etc). As far as I know, true LVDS is supported only in Bank3 for Max10 devices. Check the data sheets for LVDS support and IO Bank support.

  • NM8's avatar
    NM8
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi Abe,

    My Question is whether I can use a True LVDS in bank with VCCIO = 3.3V?

    "Plus also make sure that the IO bank you are planning to use for LVDS does support the LVDS standard (True-LVDS/BLVDS/Emulated LVDS/mini-LVDS/etc"

    Yes Its only for the TX and not for the RX. True RX is supported in all the Banks & TX count varies based on the device size.

    Kindly can anyone let me know have used a True-LVDS TX & RX (Any bank in MAX10FPGA) with VCCIO supply 3.3V?

    Thanks & Regards,

    Nanjunda M