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HWEngineer
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New ContributorMax V Clock Constraint Period
I refer to Table 3-26 Global clock period for Max V and the maximum period is not specified. When I tried setting clock constraints of 32Hz (global clock), compiler ignored the clock constraints due to invalid clock period. What is the maximum period that Max V can accept for it's Global Clock?
3 Replies
HWEngineerTable 3-26 of the Max V device handbook
Farabi_AlteraRegular Contributor
Hello,
32Hz is too slow for global clock. Can start somewhere from 5Mhz ~.
regards,
Farabi
FvMSuper Contributor
Hello,
there's no maximum clock period specified, because MAX V logic cells are fully static. As far as I'm aware of, there are no functions involving a minimal clock speed, like e.g. PLLs.
Time range of timing analysis may be restricted to 2^32 ps or something like this.
Frank
