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Using rst as clock by itself does not explain the problem but you should not do that. What drives rst. I know it is input to the module.
The quickest test is to remove that edge.
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After removing the edge the project start working, thanks :)
But warning messages still appear.
Anyway, what may be the reason to the warning messages...?
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The code in post# 1 doesn't compile due to index shift_reg row_length errors.
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Sorry, i forgot to change (for this post) generic values in entity of conv_2d_X.vhd, anyway in my project i do this by using "generic map" in top *.vhd file of the project.
I attached the correct vhdl files in post# 1, now it must compile.
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