Altera_Forum
Honored Contributor
10 years agomatrix inverse (2x2)
Hi. I'm new to VHDL. I want to write a code to get the inverse of matrix. My code is
package type_m is type row is array (0 to 1) of std_logic_vector (15 downto 0); type matrix is array (0 to 1) of row; end package type_m; entity mat_inv is port ( a : in matrix; b: out matrix); end mat_inv; architecture Behavioral of mat_inv is signal det: STD_LOGIC_VECTOR; begin det <= (a(0,0) * a(1,1)) - (a(1,0) * a(0,1)); det <= abs(std_logic_vector(det)); b(0,0) <= (1/det)*a(1,1); b(0,1) <= (1/det)*(-a(0,1)); b(1,0) <= (1/det)*(-a(1,0)); b(1,1) <= (1/det)*a(0,0); end Behavioral; But at first I get error that b is not declared. If I comment it, then it says det and std_logic_vector is not declared!!!!! I added these libraries: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use IEEE.STD_LOGIC_UNSIGNED.all; Thank you :)