Forum Discussion
Can you help to clarify few things below?
1) Does your design need to run 3 days in order to finish the compilation? Or only this happened when you used DSE?
2) Did you try analyze your design on the timing violation before using the DSE to close timing? Using DSE is one of the method to close timing, but you will need to analyze the path is that make sense to use DSE to close timing, if you have a slack that is very large, it does not make sense to use DSE to close the timing.
3) Is that fine for you to send the timing report to have a look on the failure path?
4) I am not sure what it means by full moon, may be you can make some explanation on it?
- No, it is just when using DSE and only sometimes.
- Yes, I am doing that when a slack is large, e.g. 2ns.
- Yes, I will, see below
- It occurs every month, I have been observing this for about a year. Always when full Moon (i.e. lunar phase). I know it sounds crazy but we do have that issue regularly. We do have a date stamp in our design, it comes from a server using tcl script which creates vhdl file with a date.
I mean this is not preventing us from our work except of 2-3 days a month. I will send you timing report as soon as it occurs again, next time is 18.May.