Matching timing constraints regularly fails when Full Moon

>> May be that time stamp causes that chaos ?

Hi Paul, sorry my magic bowl still at repair service so I have to struggle over and look somewhere for a cure.

Don't remember what was version when I started using Cyclone V but 12.1 seems have cyclone support, did you try'd compile on that version to see if meet timing constraint?

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2018/vulnerability-in-jtag-server-potentially-allows-a-local-attacker.html

Some issue remain open for a long time, I seen intermixing Verilog/VHDL sometimes has oddity like wrong signal propagation or signal name not assigned to, but you as me appear as using VHDL.

In the past I experienced trouble on constant conversion, sometimes where ok sometimes if then elsif else failed.

Actually I discovered VHDL 2018 sometimes fail convert , 3x"5" compare ok with "101", no warning no error but seldom havoc on code.

This forum is also bad and doesn't work searching old thread hiding knowledge.

try this link:

https://forums.intel.com/s/question/0D70P000005Peb5/is-if-elsif-else-in-this-case-errant?s1oid=00DU0000000YT3c&s1nid=0DB0P000000U1Hq&emkind=chatterCommentNotification&s1uid=0050P0000081Uem&emtm=1551062347309&fromEmail=1&s1ext=0

Actually changing constants from format 3x"hex digit" 3x"0", 3x"1", 3x"2" .. to binary "000", "001", "010"... seems mitigated, more work in progress but primary task is to finish my work on time, then i can beta test Quartus.

Last question by KTAN9, yes I am using VHDL 2008, otherwise 3x"n" is invalid syntax.

No idea when and why sometimes fail nor found how to repeat in non stocastic mode.