Matching Delimiter does not work

Hi,

I've opened a VHDL file in Altera Quartus II 10.1 (linux64) and I cannot get the Matching Delimiter feature to work.

I tried clicking the context menu and using the CTRL+M keyboard combination. I've tried placing my cursor before and after the parenthesis, selecting it, putting the cursor at a "begin" or "end" token... Nothing works.

What am I missing?

Thanks