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IPiat
New Contributor
New ContributorMaster data width is more than slave data width in Qsys AXI bridge
Hi all! Currently I am working in Quartus 17. I have created AXI bridge-based system in the Qsys, where data bus for both master and slave sizes is 32-bit. Now I need to increase AXI bridge data wid...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorTo create a custom component (or Intellectual Property (IP)) that functions using AXI bridge in Qsys, click the title below for the training video:
Custom Component Development Using Avalon® and Arm* AMBA* AXI Interfaces
