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Altera_Forum
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12 years ago

Managing One Design with Multiple FPGA Output Binaries

I have a single project that I would like to build into three FPGA images. The only difference between the FPGA images is which top level Verilog file is used. All three images have the same pin decl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Post a zip file containing your simplified code, or email it to me, and I'll take a look.

Do you have a development board? I might already have an example synthesis script you can look at.

Cheers,

Dave