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BDarji's avatar
BDarji
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Making custom component visible to Platform Designer (Qsys)

Hello all, Sometimes we have observed that our custom component (having _hw.tcl file) does not appear in Platform Designer (Qsys) IP library even after providing IP core search path via Qsys>Tools>...
BDarji's avatar
BDarji
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hello @sstrell ,

Thank you very much for your response and sorry for delay.

You are right that initially we use Platform Designer Component Editor to create _hw.tcl file and then are moving it to other location. But we are moving RTL files along with _hw.tcl file. And hence, RELATIVE path remains same.

In our case, we are used to place RTL files in hdl folder and _hw.tcl file remains in same folder in which hdl folder resides. Then, we are using following commands to add files.

add_fileset_file ./sls_i2c_mstr/i2cc_wrapper.sv       SYSTEM_VERILOG PATH ./hdl/i2cc_wrapper.sv TOP_LEVEL_FILE

add_fileset_file ./sls_i2c_mstr/i2cc_user_define.pkg.sv  SYSTEM_VERILOG PATH ./hdl/i2cc_user_define.pkg.sv

add_fileset_file ./sls_i2c_mstr/i2cc_dp_ram_mf.v  VERILOG PATH ./hdl/i2cc_dp_ram_mf.v

Do you see any issue in this?

Thank you and Have a Nice Day!

Regards,

Bhaumik

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Try an absolute path instead of a relative path. I think the issue may be that the relative path is relative to the .qsys file, not relative to the _hw.tcl file.

  • BDarji's avatar
    BDarji
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hello @sstrell ,

    Thank you for your response and continuous support.

    I do not think that relative path is an issue here because of following reasons:

    (1) Please refer following image. It states we can either use absolute or relative path.

    (2) Note that if we use 'user_component.ipx' file method I described in initial post, there is no issue. RTL files are generated properly when Qsys system is generated. Hence, I think file path is fine.

    What do you think?

    Have a Nice Day!

    Kind Regards,

    Bhaumik

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      5 years ago

      Have you tried the absolute path? This may be a bug that does not follow the documentation. I've seen it happen.

      Your .ipx solution is fine, but it's extra work you shouldn't have to do to make the IP visible.

      • BDarji's avatar
        BDarji
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Hello @sstrell ,

        Sorry for delayed response. And thank you for your response.

        I have tried absolute path. Please have a look at following:

        add_fileset_file ./sls_i2c_mstr/i2cc_wrapper.sv       SYSTEM_VERILOG PATH "E:/designs/sls/i_i2cc/trunk/master/software/setup/resources/i2c_mstr/hardware/component/hdl/i2cc_wrapper.sv" TOP_LEVEL_FILE

add_fileset_file ./sls_i2c_mstr/i2cc_user_define.pkg.sv  SYSTEM_VERILOG PATH "E:/designs/sls/i_i2cc/trunk/master/software/setup/resources/i2c_mstr/hardware/component/hdl/i2cc_user_define.pkg.sv"

add_fileset_file ./sls_i2c_mstr/i2cc_dp_ram_mf.v  VERILOG PATH "E:/designs/sls/i_i2cc/trunk/master/software/setup/resources/i2c_mstr/hardware/component/hdl/i2cc_dp_ram_mf.v"

        But unfortunately it didn't help.

        I have attached herewith one text file which shows messages which are generated by Qsys when we refresh system. See whether this gives any clue or not.

        Thank you,

        Bhaumik