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Altera_Forum's avatar
Altera_Forum
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17 years ago

LVDS Assignment in Quartus

Hi, I am using Quartus II 7.2 for programming a Stratix III device. I have an 8 channel (12 bit) LVDS input that I wish to deserialize and 2 LVDS clocks. I believe the megafunction for deserializa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Does ALT_INBUF_DIF have a VHDL implementation available for use as a component?

Or would it just be:

component ALT_INBUF_DIF

port

(

i : in std_logic;

ibar : in std_logic;

o : out std_logic

);

end component;

BR