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Altera_Forum's avatar
Altera_Forum
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14 years ago

lpm_divide, when is the output valid?

On a Cyclone IV I'm trying to use the lpm_divide module to divide an unsigned 22 bit numnerator by an unsigned 12 bit denominator. I've left the PIPELINE_DELAY parameter at 11, but I really need to k...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Does that mean that you concur that the ouput should appear X clock cycles after the inputs change where X is the LPM_PIPELINE value?

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Yes. It also means, that you can input new date each clock cycle, just keep track of the pipeline delay.