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Altera_Forum
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14 years ago

lpm_divide, when is the output valid?

On a Cyclone IV I'm trying to use the lpm_divide module to divide an unsigned 22 bit numnerator by an unsigned 12 bit denominator. I've left the PIPELINE_DELAY parameter at 11, but I really need to k...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Then the observed behaviour should never happen, presumed the design passes timing analysis. Also the SignalTap part must not create timing violations, of course.

P.S.: I assume, that you ignore the output before the initial state has propagated to the divider output, in other words for the first 11 clock cycles.