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Altera_Forum's avatar
Altera_Forum
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14 years ago

lpm_divide, when is the output valid?

On a Cyclone IV I'm trying to use the lpm_divide module to divide an unsigned 22 bit numnerator by an unsigned 12 bit denominator. I've left the PIPELINE_DELAY parameter at 11, but I really need to k...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You results are only plausible in case of a timing violation, either exceeding the clock frequency assumed in timing simulation, or changing the input values at the wrong time. The latter can easily happen in simulation, if you change the input at an arbitrary time.

Pipeline delay of 11 sounds unusually high, I see a default delay of 1 clock cycle suggested by the Megawizard. By the way, what's your clock frequency?