Looping problem faced since loops are not synthesizable. Any other way?

Yes you are right about the if statements. I don't know why i didn't see that. Thank you. I've made changes in my code according to your suggestions. And i understand now i do not need a loop anymore.

However, i am not clear about what you meant by the following:

"Next, since 'echo' is an asynchronous input, you should probably have some synchronizer chains to bring in the data into the FPGA's clock domain, or at least put some debounce logic.... not sure how clean your 'echo' signal's edge will be when it pops high."

Could you please break it down for me if possible. I'm still sort of in the learning phase. Thanks.