Looking for guidance re large team designs

Thanks to pletz and Rysc for your suggestions.

For the most part the design is schematic and vhdl with a little verilog. Unfortunately VQM is not supported for Stratix III.

We do not plan to do any cleanup of the current project.

What I would like to know is how folks manage large team based designs so as avoid conflicts between internals of the various blocks.

Is there a better way than bottom up design?

Thanks!