Looking for guidance re large team designs

You could:

a) Parameterize them, so the parameters passed in cause different behavior.

b) Use different architectures(VHDL) or just 'ifdef in Verilog the contents.

Both of those are ugly unless the parameterization makes sense for other reasons.

What I would strongly recommend is taking the time to clean up the files and give them new names that make sense based on their changes. Right now you've got multiple files with the same name, which is going to cause problems. If you even want to talk about them, how do you refer to them, i.e. it can't be "the ingress module" if there are three of them, but it would have to be "Charlie's ingress module, not Bill's", or something like that.

Anyway, the entity/module name is what makes them unique, and if you have unique files, then I would give them unique names. You're already jumping through a lot of hoops to get around this, and it's going to get worse, when fixing the names is not that difficult.