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Hi,
is your design a mixed language design ? I'm not sure, but many it is possible to flatten the sub-designs (I have to look at that), in order to get rid of the duplicated modules.
I had a similar problem with verilog netlists and I solved the problem by renaming the modules (e.g. and2_part1).
Kind regards
GPK
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Hi again,
maybe I found a simple solution for your problem. It looks like that the vqm-files you can write out are flat by default. I prepared a smal testcase for you. To my surprise it was not necessary to re-map the stratix project to stratixIII. You can enable the vqm writing under : Setting -> Compilation Process Settings -> Save a node-level netlist ....
Look into the attached project.
Kind regards
GPK
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