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I am looking for guidance from folks with experience developing and/or managing code for large FPGAs.
Our project is moving from three Stratix FPGAs to one Stratix III FPGA.
In the original design, the code for each was compiled from independent files. Not surprisingly the implementer/s copied and changed files. The result being:
1. entities with EXACTLY the same names and ports yet different architectures,
2. a few cases where the names are the same yet ports are different, and
3. lastly the same generics are used with different values.
I choose to solve this problem by using bottom up design and importing a post synthesis net list for the guts of each of the original FPGAs.
While this project is about done, I can see the problem of “duplicated” but different entities in any large team based design preventing top down compiles.
Is there a better way to solve this problem? Managing names from top to bottom does not seem practical.
Thanks!
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Hi,
is your design a mixed language design ? I'm not sure, but many it is possible to flatten the sub-designs (I have to look at that), in order to get rid of the duplicated modules.
I had a similar problem with verilog netlists and I solved the problem by renaming the modules (e.g. and2_part1).
Kind regards
GPK
Honored Contributor
