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EGrub's avatar
EGrub
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

LogicLock Arria10 issues with Platform Designer projects

I'm having a big Platform Designer project with Quartus Prime 18.1 (there is a good reason why I use this version but should not be the topic of this issue) With an Arria10 the Platform Designer ge...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi @EGrub

Here's the feedback I get from the engineering team:

Here are some things to try:

1. "*|*:calibration|*:adc"
We should try adding another (or more) leading wildcard: *| , as wildcards sometimes do not cross hierarchical boundaries.

2. Is adc is a hierarchy or bus? Try "*|*:calibration|*:adc|*" or "*|*:calibration|*:adc[*]"

3. Set logiclock region with absolute name, and fix the name whenever you re-ran platform designer.

Let me know whether it helps.

Best Regards,

Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi @EGrub

Based on the latest feedback, do you able to get it works?

Best Regards,

Richard Tan