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Altera_Forum
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12 years ago

logic utilization over 100%

Hi, I am doing some OpenCL for FPGA design with the Stratix V PCIe385_n5 board. When I compiled my kernel by aoc -c kernel.cl -report I got the result that the logic utilization is 13...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi, BadOmen

Thanks for your reply. I found the problem later. It is because that I used nested for loops, and didn't unroll them at all. The throughput was pulled down at these bottlenecks so that huge amount of registers are used to create FIFO queues to maintain the waiting data. After unrolling the loops, the kernel works fine now. Thanks again.