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Jamil's avatar
Jamil
Icon for New Contributor rankNew Contributor
4 years ago

Logic Analyzer Interface (LAI) using QUARTUS PRIME PRO 20.4

Hi FPGA community, I am trying to add a very simple logic analyzer interface (LAI) to my design. Once I did this, then I restarted the compilation. But The compilation does not go through. Nor...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

How full is your design? Even though it worked in 18.1, perhaps your design is already pretty full and changed algorithms in 20.4 are preventing a successful P&R.

  • Jamil's avatar
    Jamil
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi sstrell,

    Thanks for your reply. No the design is for sure not full. We used approx. 40% of the logic ressources (LABs) and 8% of the memeory ressources.

    BR

    Jamil