logging error in vhdl

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Why in the world would you do that? Removing the file presumably removes some input stimulus from the testbench. The problem is that files cannot be logged to a Modelsim log file, not that it is not valid VHDL.

Kevin

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As Tricky said this applies only for synthesis, for testbench it is ok, as long as you don't tell Modelsim to log the possible changes made.