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Altera_Forum
Honored Contributor
Honored ContributorLocation constraints and timing analysis
Hi everyone, I'm working on an RGMII interface implemented in a Cyclone IV E FPGA. The data input stage consists in an ALT_DDIO to recover DDR data in high-speed link, but also directly co...
Altera_ForumHonored Contributor
Honored ContributorThere are special option to enable this "Routing" layers in Chip Planner, you will need to file a service request on this
