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Altera_Forum's avatar
Altera_Forum
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10 years ago

Location constraints and timing analysis

Hi everyone, I'm working on an RGMII interface implemented in a Cyclone IV E FPGA. The data input stage consists in an ALT_DDIO to recover DDR data in high-speed link, but also directly co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi everyone,

I can't enable the view of "Routing" layers in Chip Planner. Are some FPGA families not supported? I'm using a Cyclone IV E.

Thanks in advance,

JG