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Altera_Forum
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11 years ago

Location constraints and timing analysis

Hi everyone, I'm working on an RGMII interface implemented in a Cyclone IV E FPGA. The data input stage consists in an ALT_DDIO to recover DDR data in high-speed link, but also directly co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Rysc,

Thanks for you very detailed answer and your tips :-) I'll take a look at routing and delay chains.

From compile to compile it pass/fails. Moreover I need to know with a high level of accuracy the time of incoming packet so it is required to keep the same routing for each FPGA programming file version.

Again, many thanks!

JG