Location constraints and timing analysis

Hi everyone,

I'm working on an RGMII interface implemented in a Cyclone IV E FPGA.

The data input stage consists in an ALT_DDIO to recover DDR data in high-speed link, but also directly connected logic elements in case of low-speed links.

I'd like from fitting to fitting to keep the same timings from the FPGA input pins to the ALT_DDIO registers inputs. To do so, I've constrained the RGMII clock to be on a certain clock buffer all the time. Also, I've constrained the location of the ALT_DDIO registers. As I said, for low-speed link application, some logic is directly connected to the FPGA input pins (parallel to the ALT_DDIO) so I've also constrained the first logic elements on the FPGA inputs.

With all those constraints, the path from the FPGA input pins to any of the first logic element is the same anytime.

The following figure illustrate such a signal path:

https://www.alteraforum.com/forum/attachment.php?attachmentid=10622

The following elements on the path are constrained for location:

- phy_rx_data[2]~5

- phy_rx_data[6]~2

- input_cell_h[2] (feeder is not constrained but is always placed at the same location)

- input_cell_l[2] (feeder is not constrained but is always placed at the same location)

Moreover, the clock is using the same global clock network since placed on the same clock control block.

However, when I run fitting with the same source code but different seeds, the slack for the setup time for the two registers (input_cell_l[2] and input_cell_h[2]) is different. I expected it to be the same due to the constraints!

Do I miss something? Is there something I don't understand?

I'd really appreciate any help...

Thanks in advance,

JG