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BSuma's avatar
BSuma
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5 years ago

localparam and parameter values in Synthesis report

I am writing a parameterized Verilog module. In the module I calculate some localparam values using the parameter valued passed. Please seed the code below for example. I want to know the values cal...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
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5 years ago

Hi,


Have you tried to simulate the design?


Thanks

Best regards,

KhaiY


BSuma's avatar
BSuma
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5 years ago

No, I didn't try to simulate it.

But, the code synthesizes and works when programmed to an FPGA chip.