Linux Qsys issue

Hi all, I am new to forum, I read many messages searching for a cure to my trouble but I see many suffer same and Win version is not free of trouble so I experienced this and found some hard to use workaround:

Platform:

MAX10 on BEmicro MAX 10 (learning)

Cyclon V HDS Terasic DE1SOC

Quartus II rel 15.0.2 build 153 on Linux 64 no patch (Web edition, I never upgraded old licence of full quartus cyclone II)

OS Linux Mint 17.2 64 Bit

Pc Sony Vaio Icore 7 8 GB ram

All platform refer to old QII 14 GUI and Gui on rel 15 is quite different, no big trouble on code compiling and generation but I found hard to follow Qsys project example, this is also due to problem I encountered:

Max 10 example LAB 14.0:

generating ALT PLL don't save when finished, editing hang, I found workaround of enlarging windows to avoid scrolling bar and this helped a lot, at end IP never get saved.

I obtained to enter PLL IP just hitting add button but again no chance to edit parameter, never got updated.

I also added search path but don't seems help.

Editing text file help and I got PLL configured and active, design has a lot of error unsolvable for now, I am new to this tool and this can be related to.

Some instances are forever enabled like lock output and areset input.

I observed Areset and Clock input direction are draw as output instead of input.

Clock table shown on pdf document don't exists or are different/ placed in a different menu.

NIOS is different and referred version don't exists, also parameter of close version are different (a beginner or when in learning this is confusing a lot)

Internal IP core of project are not listed on menu as shown on document.

I am stuck with two project due to this tools, I wish/need learn this tools to also integrate my IP cores. Old working tools are no more supported and this one appears to me as in alpha release and not ready for production, are some workaround or alternative to this tools?

Thank in advance

Roberto