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CFabr1
New Contributor
New ContributorLED circuit issue with CPLD and Quartus
Hi all,
I'm trying to implementing under Quartus this simple LED circuit (based on two D flip-flops) using a +5V CPLD (EPM7032)
As you can see, there are only three signals inputs to the ...
sstrell
Super Contributor
Super ContributorWhat are OPT0/2 and OPT1/3 connected to for clocking?
Also, in an FPGA, this is not a typical design. Normally you would just use a D flip-flop primitive or write code (Verilog or VHDL) to implement it. I don't know if that has any affect, but it's something to consider.
