Contributor
Super ContributorThis is old but mostly still relevant:
https://www.intel.com/content/www/us/en/programmable/support/training/course/oavl1100.html
This is newer (not sure what's going on with the description there:
https://www.intel.com/content/www/us/en/programmable/support/training/course/oaqsyssim.html
Nothing about simulating Avalon streaming, though.
ContributorI live in the UK. The "new" link says:
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Super ContributorIt's working now.
ContributorContributorIt appears to me that the event_ functions are blocking calls. The signal_ are their counter parts that be used in a process to wait on i.e process will only execute when their is activity on the signal. The example code shows that the event_ functions are being used in the VHDL code while the signal_ functions are being used in the verilog code to do the exact same thing.
ContributorThe examples in the ug_avalon_verification do not work out of the box. I took quite a lot of effort to get them to work with my ActiveHDL by making changes to the scripts inside.
By the way, whenever there is an example project from Altera/Intel, the project itself is configured for Stratix or Arria device. Why is this done? Why not put a low end device in the project settings so the project can open on most people's computer without trouble? The same applies to Qsys files in example designs.
Super ContributorI understand your concern but I don't have the answer as to why the project itself is configured for Stratix or Arria device initially.
If you somehow able to made the project work using the low end device. Feel free to share here with the community the project/qsys file.
This may helps those who may having similar issue and vice versa.
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
