LCELL removal during logic synthesis

hmm... if your lcell (or it's input and output)is observed in assignment editor select it and choose the option Netlist Optimizations -> Never Allow. if no lcell input/output are seen, take your input declaration and add keep command for example wire w1 /*synthesis syn_keep*/; to run away from synthesis. if your input is a register do this, reg r1 /*synthesis syn_preserve*/ ; or try /*synthesis syn_noprune*/; . lcells are used to force synthesis to leave you alone with your design, so if lcell gets synthesized i thinks it's more like lcell's input and output variables get synthesized and since lcell is left alone quartus gets rid of it. if in case your lcell output is floating in the air, and input never changes it's value. then quartus will certainly get rid of them no matter how hard you try. also please keep in mind that :

"Remove Redundant Logic Cells

This logic option removes redundant LCELL primitives or WYSIWYG

cells. If you turn this option On, the Compiler optimizes a circuit for area

and speed. The project-wide option is turned Off by default."

from chapter Using Quartus II Verilog HDL & VHDL Integrated Synthesis explains why should we take care about this option. it can be found in settings -> analysis and synthesis settings-> more settings button.