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Altera_Forum
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16 years ago

LCELL removal during logic synthesis

Per Quartus II help files: "An LCELL buffer always consumes one logic cell. It is not removed from a project during logic synthesis." As found elsewhere in the help files and these forums, t...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I'm mainly using VHDL descriptions with synthesis attributes to specify logic delay chains, if necessary in special cases. But as far as I see, LCELLs in a bdf design are generally kept, as specified. The first LCELL in a chain can be possibly "absorbed" by the driving LE. This may be unexpected, but isn't contradicting the specification, I think.