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Altera_Forum
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8 years ago

Latency of the loop

Would the latency of the below loop be different for switch_loop = 0 and switch_loop =1? The html report generated for the below kernel includes the latency of the global and local memory access. ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Do you mean that the multiplexer would wait for the FALSE condition although the TRUE condition execution is completed? Or does multiplexer has a fixed schedule to decide which condition is TRUE? I have attached the system viewer screenshot of kernel 1 (first post) and kernel 2. It looks like two parallel paths are not created as you told. The two conditions are in serial.