Forum Discussion
Altera_Forum
Honored Contributor
8 years agoLatency of the loop
Would the latency of the below loop be different for switch_loop = 0 and switch_loop =1? The html report generated for the below kernel includes the latency of the global and local memory access. ...
Altera_Forum
Honored Contributor
8 years agoTo make pipelining possible, conditional statements are converted into two parallel paths, both of which will be executed, and the correct output will be chosen by a multiplexer in the end. So, no, the loop latency does not depend on which condition is taken. However, the latency mentioned in the report is the MINIMUM latency WITHOUT considering stallable accesses (global memory, local memory, channels). The actual latency at run-time could be much higher due to pipeline stalls caused by such accesses.