Honored Contributor
Honored ContributorIn most cases, a simple TCO analysis won't be enough. The specific timing requirements of connected peripheral also have to be considered. In the present speed range, it's not unusual to have one or more separate PLL generated clocks to adjust the IO timing. After timing skews of FPGA, wiring and peripheral have been added, a positive window must remain.
So I doubt, if the maximum speed for a IO related application can be found without analyzing the respective peripherals timing. On the other hand, TCO shouldn't be the limiting factor then.
