Latency and Famx calcualtion

Hi Sam:

Based on your TCO timing, yes, I agree with th ~177 MHz fmax. However the limiting factor is probably not the cycle time, register to register, but the IO buffer. (TCO is Clock to Output)

So what this telling me, is you have a design that is trying to run the IO buffer at 350 Mhz, which is very difficult. (Not impossible, but very difficult depending on Board layout, and IO buffer selection)

FMAX is usually, how fast can you run, and get reliable data. Latency is how may clock cycles can does it take to propagate though the logic. (IE how many register delays)

Right now your TCO appears to be the limiting factor, so this can be improved by adding another register delay at the output, and making sure Quartus packs the output registers in the IO. Also selecting Faster IO standards helps.

Pete