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Honored Contributor
Honored ContributorLatches in frequecny divider using fsm implementation
I am new to verilog and HDL. I want to implement a N-frequency divider, which count clock ticks (pos and neg) and start the counting mechanism from the first rising edge of the input clk. In a...
Altera_ForumHonored Contributor
Honored ContributorHi Tricky,
Thank you for your reply. If I get it right, always @(clk) begin ... end or always @(*) are supported for compilation only but not for simulation and programming into FPGAs. Am I correct? Thanks
